![]() For very-large-scale integration realizations, the proposed design would be more powerful than other existing algorithms in future applications focusing on DSP, filtering, and communications.įast Fourier transform (FFT) plays an important role in digital signal processing systems. ![]() The resource utilization of combinational logic lookup tables (LUTs) and digital signal processing (DSP) blocks reduced by 11.7% and 42.5% compared with Juanget al.’s work. The proposed hardware accelerator can be implemented using a field-programmable gate array, which can operate at 48.33 MHz clock rate. The perceived advantages can be summarized as: 1) the proposed algorithm reduces the number of multiplications, additions, and coefficients by 42.3%, 33.3%, and 50%, respectively, compared with Park’s method under the settings of an M-sample complex input sequence (M = 256), and an N-point recursive DFT computation scheme (N = 64) for time hop L (L = 4) 2) by adopting the hardware-sharing scheme and the register-shifting concept, the proposed design only takes nine multipliers and 12 adders for realization. ![]() In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in the proposed design for a HDFT algorithm and its architecture. The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals.
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